1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor. More particularly, the invention relates to a semiconductor device including NAND memory cell transistors and NOR memory cell transistors formed on the same semiconductor substrate thereof and to a fabrication process therefor.
2. Description of Related Arts
A NAND ROM cell and a NOR ROM cell are typical mask ROM cells. The NAND ROM cell has a transistor row including a plurality of enhancement-type transistors and depletion-type transistors connected in series. The writing of ROM data in the NAND ROM cell is achieved by suitably arranging the enhancement-type transistors and the depletion-type transistors in the transistor row in accordance with the ROM data to be written therein. The NOR ROM cell has a transistor row including a plurality of cell transistors connected in parallel to a bit line. The writing of ROM data in the NOR ROM cell is achieved by selectively setting the threshold voltages of the transistors in the transistor row to a voltage higher than a supply voltage in accordance with the ROM data to be written therein.
In general, the NAND ROM is excellent in integration level but unsatisfactory in operating speed, while the NOR ROM is excellent in operating speed but unsatisfactory in integration level.
More specifically, the conventional NOR ROM cell requires one contact hole for every two memory cell transistors for interconnection. Therefore, a mask alignment margin should be provided for the formation of a contact hole region and a contact hole. This makes it very difficult to reduce the size of the memory cell.
To increase the integration level, NAND ROM cells have been widely used. In a NAND ROM, as described above, a plurality of cell transistors are connected in series in a transistor row, and contact holes are provided at opposite ends of the transistor row. Therefore, the integration level can be increased by connecting a greater number of cell transistors in series.
To meet a recent demand for higher density integration of memory cells, attempts have been made to reduce the dimensions of a device isolation region and a level difference in the NAND ROM.
For example, a higher density NOR ROM cell is proposed in which device isolation is achieved without the provision of a device isolation film and which has advantages of both the NAND ROM and the NOR ROM.
In the memory cell, as shown in FIG. 25(a) to FIG. 25(d) a plurality of high concentration diffusion layers 55 which are to be formed into source/drain regions and bit lines are formed in a parallel relation in a memory cell formation region of a semiconductor substrate 51, and a plurality of gate electrodes (word lines) 53 extending perpendicular to the high concentration diffusion layers 55 for the bit lines are formed on the semiconductor substrate 51 with intervention of an insulating film 52. Impurity ions having a conductivity type different from that of the source/drain regions are implanted into regions 57 not formed with the gate electrodes 53 and the high concentration diffusion layers 55. The regions 57 serve for device isolation between cell transistors a and b.
Since the memory cells having such a construction are not provided with a device isolation film such as a LOCOS film, the surface of the semiconductor substrate 51 is flat. Therefore, the gate electrodes 53 can be provided at intervals smaller than a usual workability limit for the formation of gate electrodes. The ion implantation into the device isolation regions 57 can be achieved in a self-alignment manner by using the gate electrodes 53 as a mask. Thus, this construction is effective for higher density integration of the memory cells.
To meet an increasing demand for higher capacity semiconductor devices, various attempts have been made for higher density integration.
For example, Japanese Unexamined Patent Publication No. Hei 4(1992)-10653 proposes a semiconductor device in which NOR ROM cells are formed in a staggered manner with an elevation difference as shown in FIG. 26(a) to FIG. 26(c). In a memory cell of the semiconductor device, a plurality of high concentration diffusion layers 65 which are to be formed into source/drain regions and bit lines are formed in a parallel relation in a memory cell formation region of a semiconductor substrate 61, a plurality of first-layer gate electrodes (word lines) 63 extending perpendicular to the high concentration diffusion layers 65 are provided on the semiconductor substrate 61 with intervention of a gate insulating film 62. A plurality of second-layer gate electrodes 64 extending parallel to the first-layer gate electrodes 63 are provided between the first-layer gate electrodes 63 with intervention of an insulating film 67.
In the semiconductor device having such a construction, a transistor a having a first-layer gate electrode 63 and high concentration diffusion layers 65 and 65 is directly connected to a transistor b having a second-layer gate electrode 64 and the high concentration diffusion layers 65 and 65. Therefore, the effective gate width of a transistor varies depending on whether ROM data is written in a transistor adjacent thereto. More specifically, where ROM data are written in the transistors b1 and b2 in FIG. 26(a), the gate width W1 of a transistor between the transistors b1 and b2 is the narrowest, the width W2 of a transistor adjoining only the transistor b1 or b2 is the second narrowest, and the width W3 of a transistor adjoining neither the transistor b1 nor the transistor b2 is the greatest. Thus, there are at least three gate widths. The variation in the gate width adversely affects the transistor characteristics of the memory cells.